module InstructionRegister(
input clk,
input IRWrite,
input [31:0] dIn,
//output reg [1:0] port,
output reg[5:0] instruction,
output reg[4:0] rs,
output reg[4:0] rt,
output reg[15:0] address //rd [15:11] shamt [10:6] funct [5:0] solo para R-type
);
always @(posedge clk) 
        begin
          if (IRWrite)
             begin
            //  port <= dIn[31:30];
              instruction <= dIn[31:26];
              rs<=dIn [25:21];
              rt<=dIn [20:16];
              address <= dIn [15:0]; 
             end
        end
endmodule 